DESIGN FOR TESTABILITY

Design-for-testability (DFT) techniques aim to reduce the high cost of generating test vector sequences for VLSI circuits. These techniques can also simplify the identification of faulty chips in the field. When choosing a DFT technique for a particular circuit, one must weigh the advantages of simpler test vector generation, higher fault coverage, and possibly reduced test application time against the disadvantages. No single DFT technique is optimal for all situations. Once a DFT technique has been selected, it should be consistently applied throughout the design cycle, from inception to completion.

The manufacturing of VLSI chips poses several challenges. The chips are becoming increasingly dense, with numerous transistors, making it more likely to encounter defects. Errors in the translation process can also occur due to bugs in CAD software tools. To ensure that chips are designed according to the blueprint and avoid substantial losses for the company, it is essential to detect and handle defects with appropriate diagnostics.

DFT techniques can be applied at various stages of the design and production cycle. Test structures are inserted during the design stage to measure the testability of each component. DFT can also be applied during test generation to speed up the ATPG process. During the first silicon stage, defects are detected and handled, including process problems, model errors, and pattern errors. DFT at the chip production stage helps ensure the overall quality of shipped products. Board-level and system-level tests also benefit from DFT, helping to test the operational life of chips with temperature tests and ensuring the smooth working of replaceable parts. The application of DFT throughout these stages can lead to better quality results, a faster development cycle, a better quality of product, and easier diagnostics.