RTL VERIFICATION

Design verification is a critical stage in the development of VLSI products. Its purpose is to ensure that the design of a product or system meets the required standards and specifications. Typically, design verification accounts for approximately 70% of the total time spent in the product development process.

Verification escapes, or bugs that go undetected during the design validation/verification process, are a common challenge faced by ASIC design companies. Such issues may only be identified during the silicon validation phase or when the end product is being used by the customer. These escapes can result in costly respins of the ASIC, which can significantly impact product cost and time-to-market. In some cases, multiple respins may be necessary if new issues arise after a previous respin, and hardware or software workarounds are not feasible. This paper aims to identify and discuss the underlying causes of silicon bugs in ASIC designs.