DESIGN FOR TESTABILITY

Design For Testability Course

Design for Testability is a course that focuses on techniques and methodologies used to design and develop hardware and software systems that are easily testable. This course covers the fundamental principles of testability, the types of tests that can be performed, and the trade-offs associated with designing for testability.

The course begins with an introduction to the basics of testing and testability, including the concepts of fault models, test generation, and fault simulation. The course then covers topics such as built-in self-test (BIST), boundary scan testing, and fault injection. Additionally, the course will cover the design of testable software, including unit testing, integration testing, and system testing.

The course also discusses the challenges and trade-offs associated with designing for testability. These include the impact of testability on system performance, power consumption, and cost, as well as the challenges of designing for testability in complex systems.

Course Outcomes

Upon completion of this course, students will be able to:

- Understand the principles of testability and the types of tests that can be performed
- Design hardware and software systems that are easily testable
- Understand the trade-offs associated with designing for testability
- Use techniques such as built-in self-test (BIST), boundary scan testing, and fault injection to improve testability
- Design and implement effective testing strategies for hardware and software systems

Course Outline

VLSI Basics Module

ASIC Design Flow

- Introduction to ASIC/FPGA/SOC
- ASIC Design Flow
- Manufacturing process

Introduction to Linux basics

- History of Linux
- Linux distributions and versions
- The Linux file system
- Linux command line interface

Linux Commands

- Basic Linux commands (ls, cd, mkdir, rm, cp, mv, etc.)
- Advanced Linux commands (grep, sed, awk, etc.)
- Managing processes
- Text editors (vi, nano)

Introduction to GVIM Interface

- GVIM window and buffer management
- Using modes (insert, normal, visual)
- Basic GVIM commands (save, quit, open, etc.)

GVIM Editing

- GVIM window and buffer management
- Using modes (insert, normal, visual)
- Basic GVIM commands (save, quit, open, etc.)

Basic Shell scripting

- Writing and running shell scripts
- Shell script syntax and variables
- Looping and branching statements
- Using command-line arguments in scripts

GIT Basics

- GVIM window and buffer management
- Using modes (insert, normal, visual)
- Basic GVIM commands (save, quit, open, etc.)

Collaborating with GIT

- GVIM window and buffer management
- Using modes (insert, normal, visual)
- Basic GVIM commands (save, quit, open, etc.)

Advanced GIT Features

- GVIM window and buffer management
- Using modes (insert, normal, visual)
- Basic GVIM commands (save, quit, open, etc.)

GIT Best Practices

- GVIM window and buffer management
- Using modes (insert, normal, visual)
- Basic GVIM commands (save, quit, open, etc.)

GIT Troubleshooting and maintenance.

- Git recovery and restoration
- Git troubleshooting tips and tricks
- Git maintenance and optimization for corporate use
- Git security and access control best practices

CMOS Basics

- Review of Semiconductor physics
- MOSFT Basics
- Pass Transistors
- CMOS Inverter operation and its characteristics
- CMOS Logic circuits
- CMOS Basic Building blocks
- CMOS sequential elements
- Flip flop timing Parameters – (SETUP, HOLD, CLK TO Q)

Digital Design Basics

- The importance of Number System in Data Representation.
- Different Optimization techniques using Boolean algebra.
- Gate level optimization
- Logic optimization using Karnaugh Maps.
- Basic building blocks for Combinational Logic Circuits
- implementing different Logical Expressions using the same.
- Evolution of the Sequential Elements-Latches and Flip Flops.
- Synchronous Sequential Machines-Synchronous Detectors, Counters and Register

Advanced Digital Design

- Flip Flop timing parameters
- Critical path and operating frequency of the system.
- Design of Hybrid Counters.
- Design of complex Sequence detectors.
- Design of Control FSMs based on the specifications.
- Design of Frequency synthesizers

Verilog Basics Module

Introduction to Verilog

- Concepts of top-down design
- Overview of RTL models, gate/switch models
- The RTL design flow with simulation and synthesis

Design Verification Using Simulation

- Writing verification testbenches in Verilog
- Running your preferred Verilog simulator
- Debugging designs with simulation
- Lab: Running your simulator and debug tool

Verilog HDL Syntax and Semantics

- Identifier names
- Logic values and numbers
- Data types and 2-state vs. 4-state guidelines, parameters
- Lab: Experiment with 4-state and other data types

Procedures and Assignment Statements

- Procedural blocks
- Blocking and nonblocking assignments
- Continuous assignments
- Tasks and functions
- Lab: Experiment with blocking and nonblocking assignments.

Programming Statements and Operators

- Programming statements and language rules
- Operators and language rules
- Avoiding subtle programming “gotchas” Guidelines for best coding practices
- Lab: Model and verify a simple ALU

System Verilog Compound Types and Packages

- Arrays and array assignments
- Design of simple memory blocks
- Lab: Model and verify a Dual Port RAM

Synthesizing RTL Models

- General synthesis guidelines
- Running your preferred synthesis compiler
- Lab: Synthesize a shift/storage register

RTL Models of Combinational Logic

- Always procedures and sensitivity list Continuous assignments
- Synthesis full case and parallel case statements
- System Verilog unique and priority decision statements
- Lab: Model, verify and synthesize an ALU

RTL Models of Sequential Logic

- Flip-flops and latches
- Synchronous and asynchronous inputs
- Lab: Model, verify and synthesize a Johnson counter.

Modelling State Machines

- Modelling Mealy and Moore state machines
- Modelling state encoding sequences.
- Lab: Model, verify and synthesize a UART

Introduction to Design for Testability

Definition and importance of DFT
Overview of DFT Techniques
Goals of DFT
Basics concepts and definitions

Test basics

Introduction to testing and test patterns.
Fault models
Test coverage
Test Quality metrics

Built-in Self-Test (BIST)

Introduction to BIST
BIST techniques for logic and memory
Design and implementation of BIST
BIST test pattern generation and fault coverage analysis

Scan-Based Techniques

Introduction to scan design
Scan chain insertion and test pattern generation
Scan compression and test time reduction
Advanced scan design techniques

Boundary Scan (JTAG)

Introduction to boundary scan
JTAG architecture and standard
Boundary scan test pattern generation and fault coverage analysis
Boundary scan implementation and testing

Memory Testing

- Memory testing basics
- March algorithms and memory BIST
- Memory repair techniques
- Memory redundancy and sparing

Design for Debug

- Debugging techniques and challenges
- Design for debug principles
- On-chip debug infrastructure and tools
- Debugging during production and in the field

Analog and Mixed-Signal DFT

- DFT challenges in analog and mixed-signal circuits
- Analog and mixed-signal test techniques
- Design and implementation of analog BIST and scan chains
- Mixed-signal testing and debugging

Design for Testability Tools

- DFT tools and flows
- Automatic test pattern generation (ATPG) tools
- Scan synthesis and compression tools
- Memory test and repair tools

Project-based Learning

- Practical hands-on projects to reinforce concepts learned in class.
- Real-world DFT design challenges
- Project management and teamwork