RTL Design Course
RTL design course is designed to train engineers on hardware description languages, which are used to transform specifications into RTL or behavioral descriptions. The RTL description is then translated into a gate-level netlist using synthesis tools.
Engineers who take this course will gain experience in designing digital systems. The course covers complete Verilog and System Verilog HDLs, which will help design engineers write effective behavioral descriptions for developing testbenches and RTL descriptions for hardware.
Additionally, the course covers topics such as linting, logic equivalence checking, and developing multi-clocking circuits (CDC: clock domain crossing). Timing analysis is also included to effectively identify timing violations before reaching the physical design phase to avoid large re-spins.
The outcome of this RTL design course is a deep dive into Verilog and System Verilog language semantics and the modeling of hardware circuits widely used in ASICs, SOCs, and FPGAs. Engineers will also gain experience in the tools used for synthesis, verification, CDC, linting, timing, and LEC.
Course Outcomes
Understanding of VLSI Design: Participants will gain a comprehensive understanding of the VLSI design process, including key concepts such as digital logic design, circuit optimization, timing analysis, and layout design.
Knowledge of Industry-Standard Tools: Participants will learn how to use industry-standard tools for VLSI design and verification, including Electronic Design Automation (EDA) tools such as Cadence, Synopsys, and Mentor Graphics.
Proficiency in Hardware Description Languages: Participants will become proficient in using hardware description languages (HDLs) such as Verilog and VHDL for modeling and simulating digital circuits.
Ability to Design and Verify Complex Digital Circuits: Participants will be able to design and verify complex digital circuits, including combinational and sequential circuits, finite state machines, and memory elements
Understanding of Verification Techniques: Participants will gain an understanding of verification techniques such as simulation, formal verification, and hardware emulation, and learn how to apply these techniques to ensure the correctness of their designs.
Course Outline
VLSI Basics Module
ASIC Design Flow
- Introduction to ASIC/FPGA/SOC
- ASIC Design Flow
- Manufacturing process
Introduction to Linux basics
- History of Linux
- Linux distributions and versions
- The Linux file system
- Linux command line interface
Linux Commands
- Basic Linux commands (ls, cd, mkdir, rm, cp, mv, etc.)
- Advanced Linux commands (grep, sed, awk, etc.)
- Managing processes
- Text editors (vi, nano)
Introduction to GVIM Interface
- GVIM window and buffer management
- Using modes (insert, normal, visual)
- Basic GVIM commands (save, quit, open, etc.)
GVIM Editing
- GVIM window and buffer management
- Using modes (insert, normal, visual)
- Basic GVIM commands (save, quit, open, etc.)
Basic Shell scripting
- Writing and running shell scripts
- Shell script syntax and variables
- Looping and branching statements
- Using command-line arguments in scripts
GIT Basics
- GVIM window and buffer management
- Using modes (insert, normal, visual)
- Basic GVIM commands (save, quit, open, etc.)
Collaborating with GIT
- GVIM window and buffer management
- Using modes (insert, normal, visual)
- Basic GVIM commands (save, quit, open, etc.)
Advanced GIT Features
- GVIM window and buffer management
- Using modes (insert, normal, visual)
- Basic GVIM commands (save, quit, open, etc.)
GIT Best Practices
- GVIM window and buffer management
- Using modes (insert, normal, visual)
- Basic GVIM commands (save, quit, open, etc.)
GIT Troubleshooting and maintenance.
- Git recovery and restoration
- Git troubleshooting tips and tricks
- Git maintenance and optimization for corporate use
- Git security and access control best practices
CMOS Basics
- Review of Semiconductor physics
- MOSFT Basics
- Pass Transistors
- CMOS Inverter operation and its characteristics
- CMOS Logic circuits
- CMOS Basic Building blocks
- CMOS sequential elements
- Flip flop timing Parameters – (SETUP, HOLD, CLK TO Q)
Digital Design Basics
- The importance of Number System in Data Representation.
- Different Optimization techniques using Boolean algebra.
- Gate level optimization
- Logic optimization using Karnaugh Maps.
- Basic building blocks for Combinational Logic Circuits
- implementing different Logical Expressions using the same.
- Evolution of the Sequential Elements-Latches and Flip Flops.
- Synchronous Sequential Machines-Synchronous Detectors, Counters and Register
Advanced Digital Design
- Flip Flop timing parameters
- Critical path and operating frequency of the system.
- Design of Hybrid Counters.
- Design of complex Sequence detectors.
- Design of Control FSMs based on the specifications.
- Design of Frequency synthesizers
System Verilog and Verilog for RTL Design
Introduction to Verilog and System Verilog
- Concepts of top-down design
- Overview of RTL models, gate/switch models
- The RTL design flow with simulation and synthesis
Design Verification Using Simulation
- Writing verification testbenches in Verilog
- Running your preferred Verilog simulator
- Debugging designs with simulation
- Lab: Running your simulator and debug tool
Verilog HDL Syntax and Semantics
- Identifier names
- Logic values and numbers
- Data types and 2-state vs. 4-state guidelines, Enumerated types
- User-defined types, Casting
- Lab: Experiment with 2-state and 4-state data types
System Verilog and Verilog for RTL Design
Procedures and Assignment Statements
- Procedural blocks
- System Verilog enhanced procedural blocks
- Blocking and nonblocking assignments
- Continuous assignments
- Tasks and functions
- Lab: Experiment with blocking and nonblocking assignments.
Programming Statements and Operators
- Programming statements and language rules
- Operators and language rules
- Avoiding subtle programming “gotchas” Guidelines for best coding practices
- Lab: Model and verify a simple ALU
System Verilog Compound Types and Packages
- Arrays and array assignments
- Structures and unions, Packages
- Lab: Model and verify an Instruction Stack
System Verilog Interfaces
- Using interfaces to simplify inter-module connections.
- Specifying interface views (modports)
- Using tasks and functions in interfaces
- Interfaces as an RTL modelling construct
- Lab: Model and verify a master/slave interface bus
Synthesizing RTL Models
- General synthesis guidelines
- Running your preferred synthesis compiler
- Lab: Synthesize a shift/storage register
RTL Models of Combinational Logic
- Always procedures and sensitivity list Continuous assignments
- Synthesis full case and parallel case statements
- System Verilog unique and priority decision statements
- Lab: Model, verify and synthesize an ALU
RTL Models of Sequential Logic
- Flip-flops and latches
- Synchronous and asynchronous inputs
- Lab: Model, verify and synthesize a Johnson counter.
Modelling State Machines
- Modelling Mealy and Moore state machines
- Modelling state encoding sequences.
- Lab: Model, verify and synthesize a UART
Modelling Structural Netlists—After Synthesis
- Module instantiation
- Generating arrays of instances
- Parameterized models and redefining parameters
- Verilog constructs used in ASIC/FPGA libraries.
- Delay calculation and back annotation, SDF files
- Lab: Model an ASIC netlist and use SDF back annotation
Modelling RAMs and ROMs
- Modelling memories
- Modelling bi-directional ports
- Timing constraints
- Lab: Model and verify a dual-port RAM
Basics of Linting
- Purpose of linting
- How does it work?
- Typical Lint Targets
- Tool flow and reading design
- Goal selection and setup
- Run Analysis and Debug
Clock Domain Crossing
- CDC basics, Clock domains and clock groups
- CDC synchronization techniques
- CDC problems and solutions
- Issues in CDC flow, Constraints versus Waivers
- Capturing design intent using CDC constraints
- Tool setup, Run analysis and debug.
- Abstract CDC flow
- Hierarchical waiver in SoC CDC methodology
Power Aware Design Techniques
- Introduction to Low Power
- Power Intent and UPF
- Special low power cells and requirements.
- Introduction to LP Static Check
RTL Synthesis
- Introduction to Synthesis
- Data setup for DC
- Accessing Design and library objects
- Constraints: reg to reg and I/O timing
- Constraints: Input transition and output loading
- Constraints: Multiple Clocks and exceptions
- Constraints: Complex design considerations
- Post synthesis output data
Logic Equivalence Checking
- Basic concepts of Formal verification and LEC
- Input generation for LEC
- Hands-on project
System Verilog Object Oriented Programming for Verification
Introduction to Verilog and System Verilog
- Overview and history of Verilog and System Verilog
- Synthesis and verification language subsets
- A simple Verilog test bench
- Lab: running simulations
Verilog and System Verilog Syntax and Semantics
- Identifier names
- Logic values and literal values
- Verilog and System Verilog data types
- Lab: Verification with 2-state data types
Procedures, Programming Statements and Operators
- Procedural blocks
- Tasks and functions
- Procedural assignments (blocking and non-blocking)
- Continuous assignments
- Programming statements and operators Modelling RAMs and ROMs
- Modelling memories
- Loading programs into memory models
- Lab: model and verify a single-port SRAM
System Verilog User-defined Types and Packages
- User-defined types and enumerated types
- Structures and unions
- Casting
- Packages and $unit
- Lab: Model and verify an Instruction Stack
System Verilog Interfaces
- Using interfaces to simplify inter-module connections.
- Specifying interface views (modports).
- Using tasks and functions in interfaces
- Using interfaces between the testbench and the DUT
- Lab: model and verify a master/slave interface bus
Verilog Verification Constructs
- Configurable test benches
- Structured tests
- Reading and Writing data files
- Lab: verify a design using test vectors
Program Blocks and Clocking Domains
- Program blocks
- Clocking domains
- Final blocks
- Lab: Developing a test program
Object-Oriented Programming- Part One
- System Verilog’s class data type
- Defining class objects
- Class methods
- Class inheritance
- Lab: Creating a simple OOPs testbench
Object-Oriented Programming, Part Two
- Extending class definitions (inheritance)
- Virtual methods
- Virtual classes
- Public and private classes
- Lab: Creating an advanced OO testbench
Dynamic Arrays and Scoreboards
- Dynamic arrays
- Associative arrays
- Queues
- Strings
- Lab: Create a scoreboard using dynamic arrays
Process Synchronization
- Fork—join dynamic processes.
- Built-in mailbox classes
- Built-in semaphore classes \Enhanced event data types
- Lab: Using mailboxes for verification
Constrained Random Value Generation
- Built-in System Verilog random classes
- Defining constrained random values
- Constrained random verification methodologies
- Lab: Using constrained random test values
Functional Coverage
- Defining and constructing cover groups
- Defining cover points and coverage bins
- Coverage sampling
- Cross coverage
- Lab: Using coverage with constrained random tests
Overview of System Verilog Assertion
- Assertion concepts
- Immediate and concurrent assertions
- Assertion sequence definitions
Overview of System Verilog UVM
- Importance of verification methodologies
- UVM concepts
- UVM verification component
System Verilog Assertions for Design & Verification
Introduction to System Verilog Assertions (SVA)
- A first look at System Verilog Assertions
- The traditional design processes.
- Using SVA in the definition of designs
- Using SVA in the definition of verification
- Using SVA to facilitate coverage metrics.
- Naming conventions
- Lab: Running simulations with SVA
Overview of SVA Properties and Sequences
- Immediate and concurrent assertions
- The SVA property construct
- The SVA sequence construct
- When to use properties versus sequences
- Antecedent, consequent, and threads
- Assertion, assumption, and verification directives
- Lab
Understanding Sequences
- Sequence operators and built-in functions
- Capturing temporal behaviour
- Implication operators
- First match operator
- Repetition operators
- Sequence composition operators
- Sequence methods
- Lab
Understanding Properties
- Property declaration syntax
- Using formal arguments
- Local variables in properties
- Clocking events
- Disabling condition
- Property expressions
- Property operators
- Lab
Advanced Properties and Sequences
- Data types in properties and sequences
- Proper use of assertion overlapping
- Chaining implication operators
- Multiple thread termination
- Unbounded ranges in properties
- Lab
SVA System Functions and System Tasks
- Using the $sampled system function
- Using the $past, $fell and $stable system functions
- Vector analysis system functions
- Severity level system functions
- Assertion control system tasks
- Lab
Clocked and Multi-clocked Assertions
- Clock specification for properties and sequences
- Clock resolution
- Using a default clock
- Multiple clocked sequences
- Multiple clocked properties
- Lab
Verification Directives & Verification-based Coverage
- The assert, assume and cover directives
- SVA coverage
- Coverage metrics
- Lab
Binding SVA to Design Blocks
- The SVA bind construct
- Binding to all instances of a module or interface
- Binding to a single instance of a module or interface
- Verifying VHDL models using SVA
- Lab
Assertion Verification Plans
- What goes into an assertion verification plan?
- Planning the who, what and where
- Analyzing the design specification
- Final project: Define assertions for a small Design.