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RTL VERIFICATION

RTL Verification Course

RTL verification is a process of verifying the functionality, correctness, and performance of a digital circuit or system at the register transfer level (RTL) of abstraction. The RTL level is the level at which the digital circuit is described using hardware description languages (HDL) such as Verilog or VHDL. RTL verification is an important step in the design process, as it helps to ensure that the digital circuit functions as intended before it is fabricated.

RTL verification involves developing a testbench, which is a set of input stimuli used to exercise the digital circuit under test. The testbench generates a sequence of inputs, which are applied to the circuit, and the output responses are compared to the expected output values. The goal of RTL verification is to ensure that the output responses match the expected values for all possible input sequences.

RTL verification techniques:

Directed testing: Directed testing involves designing test cases based on the designer’s understanding of the circuit’s behavior

Random testing: Random testing involves generating test cases randomly, and is useful for exploring the design space and identifying potential issues

Constraint-based testing: Constraint-based testing involves generating test cases based on specified constraints, such as input signal frequencies or amplitude ranges.

RTL verification also involves analyzing the verification coverage, which is a measure of the percentage of the design that has been tested. Coverage analysis helps to ensure that all possible scenarios and corner cases have been tested, and can help identify areas of the design that require further testing.

Overall, RTL verification is an essential step in the digital circuit design process, and helps to ensure that the final design is functional, correct, and performs as intended.

Course Outcomes

Understanding of RTL Design: Participants will gain a comprehensive understanding of RTL design concepts, including basic digital circuits, combinational and sequential logic, and timing analysis.

Proficiency in Verification Methodologies: Participants will become proficient in verification methodologies such as testbenches, coverage-driven verification, constrained random verification, and assertion-based verification.

Ability to Write Effective Testbenches: Participants will learn how to write effective testbenches using System Verilog and other verification languages to verify RTL designs.

Knowledge of Assertion-Based Verification: Participants will gain an understanding of assertion-based verification techniques and how to use them to verify RTL designs.

Ability to Analyze Coverage: Participants will learn how to analyze coverage metrics to ensure that the design has been fully tested.

Understanding of Verification Tools: Participants will become familiar with industry-standard verification tools such as UVM and OVM and learn how to use them to verify RTL designs.

Knowledge of Debugging Techniques: Participants will learn how to use debugging techniques such as waveform analysis and assertion tracing to diagnose and fix issues in RTL designs.

Overall, participants in this course will gain the knowledge and skills required to effectively verify RTL designs using industry-standard tools and methodologies, making them valuable assets in the VLSI industry.

Course Outline

VLSI Basics Module

ASIC Design Flow

    • Introduction to ASIC/FPGA/SOC
    • ASIC Design Flow
    • Manufacturing process

Introduction to Linux basics

    • History of Linux
    • Linux distributions and versions
    • The Linux file system
    • Linux command line interface

Linux Commands

    • Basic Linux commands (ls, cd, mkdir, rm, cp, mv, etc.)
    • Advanced Linux commands (grep, sed, awk, etc.)
    • Managing processes
    • Text editors (vi, nano)

Introduction to GVIM Interface

    • GVIM window and buffer management
    • Using modes (insert, normal, visual)
    • Basic GVIM commands (save, quit, open, etc.)

GVIM Editing

    • GVIM window and buffer management
    • Using modes (insert, normal, visual)
    • Basic GVIM commands (save, quit, open, etc.)

Basic Shell scripting

    • Writing and running shell scripts
    • Shell script syntax and variables
    • Looping and branching statements
    • Using command-line arguments in scripts

 GIT Basics

    • GVIM window and buffer management
    • Using modes (insert, normal, visual)
    • Basic GVIM commands (save, quit, open, etc.)

 Collaborating with GIT

    • GVIM window and buffer management
    • Using modes (insert, normal, visual)
    • Basic GVIM commands (save, quit, open, etc.)

 Advanced GIT Features

    • GVIM window and buffer management
    • Using modes (insert, normal, visual)
    • Basic GVIM commands (save, quit, open, etc.)

 GIT Best Practices

    • GVIM window and buffer management
    • Using modes (insert, normal, visual)
    • Basic GVIM commands (save, quit, open, etc.)

GIT Troubleshooting and maintenance.

    • Git recovery and restoration
    • Git troubleshooting tips and tricks
    • Git maintenance and optimization for corporate use
    • Git security and access control best practices

CMOS Basics

    • Review of Semiconductor physics
    • MOSFT Basics
    • Pass Transistors
    • CMOS Inverter operation and its characteristics
    • CMOS Logic circuits
    • CMOS Basic Building blocks
    • CMOS sequential elements
    • Flip flop timing Parameters – (SETUP, HOLD, CLK TO Q)

Digital Design Basics

    • The importance of Number System in Data Representation.
    • Different Optimization techniques using Boolean algebra.
    • Gate level optimization
    • Logic optimization using Karnaugh Maps.
    • Basic building blocks for Combinational Logic Circuits
    • implementing different Logical Expressions using the same.
    • Evolution of the Sequential Elements-Latches and Flip Flops.
    • Synchronous Sequential Machines-Synchronous Detectors, Counters and Register

Advanced Digital Design

    • Flip Flop timing parameters
    • Critical path and operating frequency of the system.
    • Design of Hybrid Counters.
    • Design of complex Sequence detectors.
    • Design of Control FSMs based on the specifications.
    • Design of Frequency synthesizers

 Verilog and System Verilog Basics

Introduction to Verilog and System Verilog

    • Concepts of top-down design
    • Overview of RTL models, gate/switch models
    • The RTL design flow with simulation and synthesis 

Design Verification Using Simulation

    • Writing verification testbenches in Verilog
    • Running your preferred Verilog simulator
    • Debugging designs with simulation
    • Lab: Running your simulator and debug tool

Verilog HDL Syntax and Semantics 

    • Identifier names
    • Logic values and numbers
    • Data types and 2-state vs. 4-state guidelines, Enumerated types
    • User-defined types, Casting
    • Lab: Experiment with 2-state and 4-state data types

Procedures and Assignment Statements

    • Procedural blocks
    • System Verilog enhanced procedural blocks
    • Blocking and nonblocking assignments
    • Continuous assignments
    • Tasks and functions
    • Lab: Experiment with blocking and nonblocking assignments.

Programming Statements and Operators

    • Programming statements and language rules
    • Operators and language rules
    • Avoiding subtle programming “gotchas” Guidelines for best coding practices
    • Lab: Model and verify a simple ALU

 System Verilog Compound Types and Packages

    • Arrays and array assignments
    • Structures and unions, Packages
    • Lab: Model and verify an Instruction Stack

 System Verilog Interfaces

    • Using interfaces to simplify inter-module connections.
    • Specifying interface views (modports)
    • Using tasks and functions in interfaces
    • Interfaces as an RTL modelling construct
    • Lab: Model and verify a master/slave interface bus

 Synthesizing RTL Models

    • General synthesis guidelines
    • Running your preferred synthesis compiler
    • Lab: Synthesize a shift/storage register

 RTL Models of Combinational Logic

    • Always procedures and sensitivity list Continuous assignments
    • Synthesis full case and parallel case statements
    • System Verilog unique and priority decision statements
    • Lab: Model, verify and synthesize an ALU

 RTL Models of Sequential Logic

    • Flip-flops and latches
    • Synchronous and asynchronous inputs
    • Lab: Model, verify and synthesize a Johnson counter.

Modelling State Machines

    • Modelling Mealy and Moore state machines
    • Modelling state encoding sequences.
    • Lab: Model, verify and synthesize a UART

System Verilog Object Oriented Programming for Verification

System Verilog Assertions for Design & Verification

Introduction to Verilog and System Verilog

    • Overview and history of Verilog and System Verilog
    • Synthesis and verification language subsets
    • A simple Verilog test bench
    • Lab: running simulations

Verilog and System Verilog Syntax and Semantics

    • Identifier names 
    • Logic values and literal values 
    • Verilog and System Verilog data types 
    • Lab: Verification with 2-state data types

Procedures, Programming Statements and Operators

    • Procedural blocks
    • Tasks and functions
    • Procedural assignments (blocking and non-blocking)
    • Continuous assignments
    • Programming statements and operators
    • Modeling RAMs and ROMs
    • Modeling memories
    • Loading programs into memory models
    • Lab: model and verify a single-port SRAM

System Verilog User-defined Types and Packages

    • User-defined types and enumerated types
    • Structures and unions
    • Casting
    • Packages and $unit
    • Lab: Model and verify an Instruction Stack

System Verilog Interfaces

    • Using interfaces to simplify inter-module connections.
    • Specifying interface views (modports).
    • Using tasks and functions in interfaces
    • Using interfaces between the testbench and the DUT
    • Lab: model and verify a master/slave interface bus

 Verilog Verification Constructs

    • Configurable test benches
    • Structured tests
    • Reading and Writing data files
    • Lab: verify a design using test vectors

 Program Blocks and Clocking Domains

    • Program blocks
    • Clocking domains
    • Final blocks
    • Lab: Developing a test program

Object-Oriented Programming- Part One

    • System Verilog’s class data type
    • Defining class objects
    • Class methods
    • Class inheritance
    • Lab: Creating a simple OOPs testbench

 Object-Oriented Programming, Part Two

    • Extending class definitions (inheritance)
    • Virtual methods
    • Virtual classes
    • Public and private classes
    • Lab: Creating an advanced OO testbench

Dynamic Arrays and Scoreboards

    • Dynamic arrays
    • Associative arrays
    • Queues
    • Strings 
    • Lab: Create a scoreboard using dynamic arrays

 Process Synchronization

    • Fork—join dynamic processes.
    • Built-in mailbox classes
    • Built-in semaphore classes \Enhanced event data types
    • Lab: Using mailboxes for verification

Constrained Random Value Generation

    • Built-in System Verilog random classes
    • Defining constrained random values
    • Constrained random verification methodologies
    • Lab: Using constrained random test values

 Functional Coverage

    • Defining and constructing cover groups
    • Defining cover points and coverage bins
    • Coverage sampling
    • Cross coverage
    • Lab: Using coverage with constrained random tests

Introduction to System Verilog Assertions (SVA)

    • A first look at System Verilog Assertions
    • The traditional design processes.
    • Using SVA in the definition of designs
    • Using SVA in the definition of verification
    • Using SVA to facilitate coverage metrics.
    • Naming conventions
    • Lab: Running simulations with SVA

 Overview of System Verilog Assertion

    • Assertion concepts
    • Immediate and concurrent assertions
    • Assertion sequence definitions

 Overview of SVA Properties and Sequences

    • Immediate and concurrent assertions
    • The SVA property construct
    • The SVA sequence construct
    • When to use properties versus sequences
    • Antecedent, consequent, and threads
    • Assertion, assumption, and verification directives
    • Lab

Understanding Sequences

    • Sequence operators and built-in functions
    • Capturing temporal behaviour
    • Implication operators
    • First match operator
    • Repetition operators
    • Sequence composition operators
    • Sequence methods
    • Lab

 Understanding Properties

    • Property declaration syntax
    • Using formal arguments
    • Local variables in properties
    • Clocking events
    • Disabling condition
    • Property expressions
    • Property operators
    • Lab

Advanced Properties and Sequences

    • Data types in properties and sequences
    • Proper use of assertion overlapping
    • Chaining implication operators
    • Multiple thread termination
    • Unbounded ranges in properties
    • Lab

SVA System Functions and System Tasks

    • Using the $sampled system function
    • Using the $past, $fell and $stable system functions
    • Vector analysis system functions
    • Severity level system functions
    • Assertion control system tasks
    • Lab

Clocked and Multi-clocked Assertions

    • Clock specification for properties and sequences
    • Clock resolution
    • Using a default clock
    • Multiple clocked sequences
    • Multiple clocked properties
    • Lab

Verification Directives & Verification-based Coverage

    • The assert, assume and cover directives
    • SVA coverage
    • Coverage metrics
    • Lab

 Binding SVA to Design Blocks

    • The SVA bind construct
    • Binding to all instances of a module or interface
    • Binding to a single instance of a module or interface
    • Verifying VHDL models using SVA
    • Lab

  Assertion Verification Plans

    • What goes into an assertion verification plan?
    • Planning the who, what and where
    • Analyzing the design specification
    • Final project: Define assertions for a small Design.

Universal Verification Methodologies

UVM Overview

    • Importance of verification methodologies
    • The purpose of UVM
    • UVM concepts
    • UVM Verification component
    • UVM testbench architecture
    • UVM test phases
    • UVM objects and components
    • Lab: Simulate a simple UVM testbench and DUT

Rapid Review of System Verilog Object-Oriented Verification

    • System Verilog’s class data type and new() constructors
    • Inheritance, data hiding.
    • Virtual methods and polymorphism
    • Specialized (parameterized) classes.
    • Object handle assignments and downcasting.
    • Constrained random value generation.
    • Functional coverage

UVM First Look

    • UVM class library
    • uvm_object class
    • uvm_component class
    • Registering UVM components with the factory
    • Virtual interfaces and connecting to the DUT.
    • UVM print and debug utilities.
    • Lab: The big picture — examine all the parts of a complete UVM testbench

UVM Sequence items and Sequences

    • UVM sequence_items (transactions)
    • Defining sequence_item methods
    • Using sequence_item field macros
    • UVM sequences of transactions
    • Sequence/Driver synchronization
    • Lab: Define and simulate sequence_items and sequences
    • UVM Sequencers and Drivers
    • UVM sequencers
    • UVM drivers
    • Transaction Level Modeling (TLM)
    • TLM ports, exports, and analysis ports
    • Lab: Define and simulate a UVM driver and sequencer

UVM Monitors and Agents

    • UVM monitors.
    • Adding one or more monitor analysis ports
    • UVM agents
    • Agent active and passive modes
    • Lab: Defining and simulating a UVM monitor and agent

UVM Functional Coverage

    • A review of System Verilog functional coverage
    • Coverage collectors
    • Where to add coverage collectors
    • Enabling and disabling coverage collectors
    • Lab: Define, simulate, and examine coverage
    • UVM Environments, Predictors, and Scoreboards
    • Scoreboard fundamentals
    • Predicting expected results
    • Comparing expected and actual results
    • Encapsulation in a test environment
    • Lab: Define and simulate a UVM scoreboard and environment, and verify the outputs of a (faulty) DUT

UVM Tests and Advanced Sequences

    • Putting everything together in a UVM test
    • Running multiple tests
    • Virtual sequences and sequencers
    • Sequential and parallel sequences
    • Sequencer arbitration modes
    • Layered sequences.
    • Driver to sequence feedback
    • Top-level modules
    • Lab: Define and simulate a test that runs multiple
    • sequences

UVM Factory and UVM Configuration

    • Understanding the UVM factory
    • Registering and constructing verification components
    • Factory overrides
    • Using the UVM Configuration database
    • Reuse and scalability considerations
    • UVM messages and reports
    • Lab: Define and simulate a configurable UVM test environment
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